DhruvalMistry
I design clocked digital hardware in SystemVerilog. This project is a register-mapped programmable timer that counts on every clock, detects overflow, reloads automatically and raises a maskable interrupt request, the same building block that sits inside every microcontroller and SoC.
ProgrammableTimer and Interrupt Controller
A synthesizable timer IP in SystemVerilog. Load a value, start the counter, catch the overflow, reload and interrupt, all controlled through registers.
Built to count
and to interrupt
Project at a glance
| Design type | Programmable timer IP |
| Language | SystemVerilog (RTL) |
| Logic style | Sequential, clocked |
| Control | Register-mapped: start, stop, enable, disable |
| Configuration | Load value and reload value |
| Event | Overflow detection |
| Output | Interrupt request |
| Flow | Verilator, GTKWave, Yosys |
Objectives
- Reusable timer IP in SystemVerilog
- Register-mapped start, stop, enable, disable
- Configurable load and reload values
- Overflow detect with automatic reload
- Maskable interrupt request
Why it matters
Almost every microcontroller and SoC carries programmable timers with interrupts. Building one exercises the core RTL skills: register control, sequential logic, event detection and interrupt handling.
supported functions
Toolchain
License
Signal chain
Follow the event from the register write to the interrupt pin. Toggle blocks to see which parts of the path go quiet.
Program it like
software would
Pick a register and tap a bit field. Layout shown is an illustrative convention, the exact map lives in the RTL.
Count, overflow, IRQ
Reset, load, run, mask the interrupt, stop and restart. Hover for values, scroll to zoom.
This trace is generated by the in-page JavaScript model. Drop a real simulator dump at data/timer.vcd and it is loaded automatically in its place.
Drive the timer
Configure load and reload values, then run it cycle by cycle. A behavioral model of the design, not simulator output.
Event log
Events: 0 overflows
Edit the RTL
Starter module and testbench you can edit. Compile and run needs a simulator service, which is not attached to this static site.
Starter code is untested example code. Verify it with your own simulator before relying on it.
Console
Test plan
Scenarios planned for the timer. Status shows PENDING until real results are added to data/results.json.
| # | Scenario | What is checked | Status |
|---|
Coverage
Inside the count
Each clock edge moves the counter through compare, increment and reload. Step it and watch the stages light up.
ENABLED AND RUNNING
enable & runCOMPARE
count == maxINCREMENT
count + 1RELOAD
count = reloadINTERRUPT
ovf & irq_enBehavioral model for illustration. Up-counter convention assumed.
From RTL to gates
read_verilog -svParse the SystemVerilog sourcehierarchy, procResolve the design and processesopt, fsm, memoryClean and simplify logicstatCell and flip-flop counts